A study about FPGA-based digital filters
Entity
UAM. Departamento de Ingeniería InformáticaPublisher
Institute of Electrical and Electronics EngineersDate
1998Citation
10.1109/SIPS.1998.715782
IEEE Workshop on Signal Processing Systems, SIPS 1998, IEEE, 1998. 192-201
ISSN
1520-6130ISBN
0-7803-4997-0DOI
10.1109/SIPS.1998.715782Editor's Version
http://dx.doi.org/10.1109/SIPS.1998.715782Subjects
Informática; TelecomunicacionesNote
Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. J. Valls, M. M. Peiró, T. Sansaloni, and E. Boemo, "A study about FPGA-based digital filters", in IEEE Workshop on Signal Processing Systems, 1998, p. 192-201Rights
© 1998 IEEEAbstract
A set of operators suitable for digit-serial FIR filtering is presented. The canonical and inverted forms are studied. In each of these structures both the symmetrical and anti-symmetrical particular cases are also covered. All circuits have been implemented using an EPF10K50 Altera FPGA. The main results show that the canonical form presents less occupation and higher throughput. The 8-tap filter versions implemented can be applied in real-time processing with sample rate ranging up to 7 MHz using the bit-serial versions and up to 25 MHz with the bit-parallel ones
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Google Scholar:Valls, Javier
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Peiró, Marcos M.
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Sansaloni, T.
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Boemo Svcalvinoni, Eduardo Iván
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