Some experiments about wave pipelining on FPGA's

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dc.contributor.author Boemo, Eduardo I.
dc.contributor.author López-Buedo, Sergio
dc.contributor.author Meneses, Juan M.
dc.contributor.other UAM. Departamento de Ingeniería Informática es_ES
dc.date.accessioned 2015-06-22T14:41:45Z
dc.date.available 2015-06-22T14:41:45Z
dc.date.issued 1998
dc.identifier.citation IEEE Transactions on Very Large Scale Integration Systems 6.2 (1998): 232-237 en_US
dc.identifier.issn 1063-8210 (print) en_US
dc.identifier.issn 1557-9999 (online) en_US
dc.identifier.uri http://hdl.handle.net/10486/666966
dc.description Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. E. I. Boemo, S. López-Buedo, and J. M. Meneses, "Some experiments about wave pipelining on FPGA's", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v. 6, n. 2, p. 232 - 237 en_US
dc.description.abstract Wave pipelining offers a unique combination of high speed, low latency, and moderate power consumption. The construction of wave pipelines is benefited by the use of gates and buffers with data-independent delays and the knowledge of the interconnection delays. These two features are present in several SRAM-based field programmable gate arrays (FPGA's): look-up tables (LUT's) allow the designer to mask the delay of different gates and combinational functions, and the timing characteristics of each wire segment are a priori known. This work describes a set of experiments about wave pipelining on FPGA's. The results show that a 13-LUT logic depth circuit mapped on an XC4005PC84-6 runs as high as 85 MHz (single phase clocking) or 80 MHz (intentionally skewed clocking), exhibiting a latency of 95 ns. This high throughput/latency ratio is unattainable using classic pipelining. en_US
dc.description.sponsorship This work was supported by the CICYT of Spain under Contract TIC95-0971. en_US
dc.format.extent 6 pág. es_ES
dc.format.mimetype application/pdf en
dc.language.iso eng en
dc.publisher Institute of Electrical and Electronics Engineers en_US
dc.relation.ispartof IEEE Transactions on Very Large Scale Integration Systems en_US
dc.rights © 1998 IEEE en_US
dc.subject.other Arithmetic en_US
dc.subject.other High performance en_US
dc.subject.other Low-power design en_US
dc.subject.other Performance tradeoffs en_US
dc.title Some experiments about wave pipelining on FPGA's en_US
dc.type article en_US
dc.subject.eciencia Informática es_ES
dc.subject.eciencia Telecomunicaciones es_ES
dc.relation.publisherversion http://dx.doi.org/10.1109/92.678876
dc.identifier.doi 10.1109/92.678876
dc.identifier.publicationfirstpage 232
dc.identifier.publicationissue 2
dc.identifier.publicationlastpage 237
dc.identifier.publicationvolume 6
dc.type.version info:eu-repo/semantics/acceptedVersion en
dc.contributor.group Laboratorio de Microelectrónica es_ES
dc.rights.accessRights openAccess en
dc.authorUAM Boemo Svcalvinoni, Eduardo Iván (259594)


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