Low-power FSMs in FPGA: Encoding alternatives

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dc.contributor.author Sutter, Gustavo D.
dc.contributor.author Todorovich, Elías
dc.contributor.author López-Buedo, Sergio
dc.contributor.author Boemo, Eduardo I.
dc.contributor.other UAM. Departamento de Ingeniería Informática es_ES
dc.date.accessioned 2015-06-23T14:45:19Z
dc.date.available 2015-06-23T14:45:19Z
dc.date.issued 2002
dc.identifier.citation Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation: 12th International Workshop, PATMOS 2002 Seville, Spain, September 11–13, 2002 Proceedings. Lecture Notes in Computer Science, Volumen 2415. Springer, 2002. 363-370. en_US
dc.identifier.isbn 978-3-540-44143-4 (print) en_US
dc.identifier.isbn 978-3-540-45716-9 (online) en_US
dc.identifier.issn 0302-9743 (print) en_US
dc.identifier.issn 1611-3349 (online) en_US
dc.identifier.uri http://hdl.handle.net/10486/667004
dc.description The final publication is available at Springer via http://dx.doi.org/10.1007/3-540-45716-X_36 en_US
dc.description Proceedings of 12th International Workshop, PATMOS 2002 Seville, Spain, September 11–13, 2002 en_US
dc.description.abstract In this paper, the problem of state encoding of FPGA-based synchronous finite state machines (FSMs) for low-power is addressed. Four codification schemes have been studied: First, the usual binary encoding and the One-Hot approach suggested by the FPGA vendor; then, a code that minimizes the output logic; finally, the so-called Two-Hot code strategy. FSMs of the MCNC and PREP benchmark suites have been analyzed. Main results show that binary state encoding fit well with small machines (up to 8 states), meanwhile One-Hot is better for large FSMs (over 16 states). A power saving of up to the 57% can be achieved selecting the appropriate encoding. An areapower correlation has been observed in spite of the circuit or encoding scheme. Thus, FSMs that make use of fewer resources are good candidates to consume less power. en_US
dc.description.sponsorship Ministry of Science of Spain, under Contract TIC2001-2688-C03-03, has supported this work. Additional funds have been obtained from Projects 658001 and 658004 of the Fundación General de la Universidad Autónoma de Madrid. en_US
dc.format.extent 9 pág. es_ES
dc.format.mimetype application/pdf en
dc.language.iso eng en
dc.publisher Springer Berlin Heidelberg
dc.relation.ispartof Lecture Notes in Computer Science en_US
dc.rights © Springer-Verlag Berlin Heidelberg 2002
dc.subject.other Computer Hardware en_US
dc.subject.other Processor Architectures en_US
dc.subject.other System Performance and Evaluation en_US
dc.title Low-power FSMs in FPGA: Encoding alternatives en_US
dc.type conferenceObject en
dc.type bookPart en
dc.subject.eciencia Informática es_ES
dc.subject.eciencia Telecomunicaciones es_ES
dc.relation.publisherversion http://dx.doi.org/10.1007/3-540-45716-X_36
dc.identifier.doi 10.1007/3-540-45716-X_36
dc.identifier.publicationfirstpage 363
dc.identifier.publicationlastpage 370
dc.identifier.publicationvolume 2451
dc.relation.eventdate September 11–13, 2002 en_US
dc.relation.eventnumber 12
dc.relation.eventplace Seville (Spain) en_US
dc.relation.eventtitle 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, PATMOS 2002 en_US
dc.type.version info:eu-repo/semantics/acceptedVersion en
dc.rights.accessRights openAccess en
dc.authorUAM Boemo Svcalvinoni, Eduardo Iván (259594)
dc.authorUAM Todorovich Stipanovich, Elías (260715)
dc.authorUAM Sutter Capristo, Gustavo Daniel (260809)

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