A tool for activity estimation in FPGAs

Todorovich, Elías; Gilabert, M.; Sutter Capristo, Gustavo Daniel; López Buedo, Sergio; Boemo Svcalvinoni, Eduardo Iván

UAM_Biblioteca

dc.contributor.author	Todorovich, Elías
dc.contributor.author	Gilabert, M.
dc.contributor.author	Sutter Capristo, Gustavo Daniel
dc.contributor.author	López Buedo, Sergio
dc.contributor.author	Boemo Svcalvinoni, Eduardo Iván
dc.contributor.other	UAM. Departamento de Ingeniería Informática	es_ES
dc.date.accessioned	2015-06-23T14:50:26Z
dc.date.available	2015-06-23T14:50:26Z
dc.date.issued	2002
dc.identifier.citation	Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream: 12th International Conference, FPL 2002 Montpellier, France, September 2–4, 2002 Proceedings. Lecture Notes in Computer Science, Volumen 2438. Springer, 2002. 340-349.	en_US
dc.identifier.isbn	978-3-540-44108-3 (print)	en_US
dc.identifier.isbn	978-3-540-46117-3 (online)	en_US
dc.identifier.issn	0302-9743 (print)	en_US
dc.identifier.issn	1611-3349 (online)	en_US
dc.identifier.uri	http://hdl.handle.net/10486/667005
dc.description	The final publication is available at Springer via http://dx.doi.org/10.1007/3-540-46117-5_36	en_US
dc.description.abstract	In this paper, an activity estimation tool for FPGA-based combinational circuits is presented. The current version is able to estimate average activity for individual nodes. The tool is statistical-based, allowing the user to specify the tolerated error at a given confidence level. The tunable properties of the implemented technique have been carefully tested, demonstrating how the designer can control the accuracy-speed trade-off. The importance of a realistic input pattern characterization has also been verified.	en_US
dc.description.sponsorship	Spanish Ministry of Science and Technology has supported this work, under Contract TIC2001-2688-C03-03. Additional funds have been obtained from Project 658001 of the Fundación General de la Universidad Autónoma de Madrid. G. Sutter and E. Todorovich are granted by CONICET of Argentine.	en_US
dc.format.extent	11 pág.	es_ES
dc.format.mimetype	application/pdf	en
dc.language.iso	eng	en
dc.publisher	Springer Berlin Heidelberg
dc.relation.ispartof	Lecture Notes in Computer Science	en_US
dc.rights	© Springer-Verlag Berlin Heidelberg 2002
dc.subject.other	Logic Design	en_US
dc.subject.other	Memory Structures	en_US
dc.subject.other	Processor Architectures	en_US
dc.title	A tool for activity estimation in FPGAs	en_US
dc.type	conferenceObject	en
dc.type	bookPart	en
dc.subject.eciencia	Informática	es_ES
dc.subject.eciencia	Telecomunicaciones	es_ES
dc.relation.publisherversion	http://dx.doi.org/10.1007/3-540-46117-5_36
dc.identifier.doi	10.1007/3-540-46117-5_36
dc.identifier.publicationfirstpage	340
dc.identifier.publicationlastpage	349
dc.identifier.publicationvolume	2438
dc.relation.eventdate	September 2–4, 2002	en_US
dc.relation.eventnumber	12
dc.relation.eventplace	Montpellier (France)	en_US
dc.relation.eventtitle	12th International Conference on Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream, FPL 2002	en_US
dc.type.version	info:eu-repo/semantics/acceptedVersion	en
dc.rights.accessRights	openAccess	en
dc.authorUAM	Boemo Svcalvinoni, Eduardo Iván (259594)
dc.authorUAM	Todorovich Stipanovich, Elías (260715)
dc.authorUAM	Sutter Capristo, Gustavo Daniel (260809)
dc.facultadUAM	Escuela Politécnica Superior