Hardware-in-the-loop using parametrizable fixed point notation
Entity
UAM. Departamento de Tecnología Electrónica y de las ComunicacionesPublisher
Institute of Electrical and Electronics Engineers Inc.Date
2016-06-27Citation
10.1109/COMPEL.2016.7556670
2016 IEEE 17th Workshop on Control and Modeling for Power Electronics (COMPEL). IEEE, 2016. 7556670
ISBN
978-150-901-815-4DOI
10.1109/COMPEL.2016.7556670Funded by
This work has been supported by the Spanish Ministerio de Economía y Competitividad under project TEC2013-43017-RProject
Gobierno de España. TEC2013-43017-REditor's Version
http://dx.doi.org/10.1109/COMPEL.2016.7556670Subjects
FPGA; Hardware-in-the-loop; Real-time simulation; TelecomunicacionesNote
Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. A. Sanchez, I. Villar, A. de Castro, F. López Colino and J. Garrido, "Hardware-in-the-loop using parametrizable fixed point notation," 2016 IEEE 17th Workshop on Control and Modeling for Power Electronics (COMPEL), Trondheim, 2016, pp. 1-6. doi: 10.1109/COMPEL.2016.7556670Rights
© 2016 IEEEAbstract
The verification of digital regulators designed to
control power converters is not trivial because the plant is analog
while the regulator is digital. There are several methodologies
to accomplish this task, but there is no standard method and,
usually, the verification is a slow process. An alternative is to
use an HIL (Hardware-in-the-loop) system which emulates in
hardware a digital model of the plant, achieving significantly
faster simulations. This paper explains how to implement a simple
but fast mathematical model for a full-bridge converter and how
to implement it using paramatrizable fixed point arithmetic.
Fixed point arithmetic is able to achieve faster simulations
compared to floating point while using less hardware resources.
This paper shows that this model can emulate the converter in
real-time using a time step of 23 ns.
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Google Scholar:Sánchez González, Alberto
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Villar Gómara, Irene
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Castro, Ángel de
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López Colino, Fernando Jesús
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Garrido Salas, Javier
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