Analysis of Xilinx SDNet tool for packet filtering in 100 Gbps network monitoring applications
Author
Fuentes de Uña, SergioEntity
UAM. Departamento de Ingeniería InformáticaDate
2018-06Subjects
sdnet; fpga; packet; Informática; MatemáticasEsta obra está bajo una licencia de Creative Commons Reconocimiento-NoComercial-SinObraDerivada 4.0 Internacional.
Abstract
Network traffic monitoring is becoming more and more challenging due to the relentless
increase in network speeds. At 100 Gbps, the classical approach of storing all traffic
for a later analysis might not be feasible, since the huge volume of data that needs to be
saved could make it impossible. Nevertheless, packet filtering allows network monitoring
tools to focus on a certain problem, discarding all packets that are not relevant for
the analysis and thus easing storage requirements. The high performance and guaranteed
line-rate operation of FPGA-based solutions make them optimal for packet filtering
at 100 Gbps. However, the effort required by a conventional, HDL-based FPGA development
methodology might be prohibitive. To address this problem, in this work we
have analyzed the results obtained with the Xilinx SDNet high-level tool for two packet
filtering cases. These two filters are related to the monitoring of sites visited by network
users and, for both cases, the SDNet designs were able to operate at line rate on actual
100 Gbps Ethernet links. SDNet results were also compared to HDL implementations
made by an experienced engineer. Though HDL-based designs allow for reduced latency
and resource utilization, SDNet excels in terms of productivity: the description of
the most complex filter only takes about 100 lines of SDNet code, that is, significantly less
than the HDL counterpart. While pushing the limits of the SDNet architecture, related
systems from the field of Queuing Theory were also modeled and studied.
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