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Now showing items 1-6 of 6
Fast FPGA-based pipelined digit-serial/parallel multipliers
Valls, Javier; Sansaloni, T.; Peiró, Marcos M.; Boemo Svcalvinoni, Eduardo Iván
1999
1999
A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation
Peiró, Marcos M.; Valls, Javier; Sansaloni, T.; Pascual, A.P.; Boemo Svcalvinoni, Eduardo Iván
1999
1999
Design and FPGA implementation of digit-serial FIR filters
Valls, Javier; Peiró, Marcos M.; Sansaloni, T.; Boemo Svcalvinoni, Eduardo Iván
1998
1998
A study about FPGA-based digital filters
Valls, Javier; Peiró, Marcos M.; Sansaloni, T.; Boemo Svcalvinoni, Eduardo Iván
1998
1998
Some notes on power management on FPGA-based systems
Boemo Svcalvinoni, Eduardo Iván; González de Rivera Peces, Guillermo José; López Buedo, Sergio; Meneses, Juan M.
1995
; González de Rivera Peces, Guillermo José; López Buedo, Sergio; Meneses, Juan M.
1995
Thermal monitoring on FPGAs using ring-oscillators
Boemo Svcalvinoni, Eduardo Iván; López Buedo, Sergio
1997
; López Buedo, Sergio
1997