dc.contributor.author | García Ávila Fernández, Alejandro | |
dc.contributor.author | Castro, Ángel de | |
dc.contributor.author | Muñoz García, Óscar | |
dc.contributor.author | Azcondo, Francisco Javier | |
dc.contributor.other | UAM. Departamento de Tecnología Electrónica y de las Comunicaciones | es_ES |
dc.date.accessioned | 2015-04-21T15:48:39Z | |
dc.date.available | 2015-04-21T15:48:39Z | |
dc.date.issued | 2009 | |
dc.identifier.citation | 35th Annual Conference of IEEE Industrial Electronics, IECON 2009, EEE, 2009, 2955-2960 | en_US |
dc.identifier.isbn | 978-1-4244-4650-6 (online) | en_US |
dc.identifier.isbn | 978-1-4244-4648-3 (print) | en_US |
dc.identifier.issn | 1553-572X | |
dc.identifier.uri | http://hdl.handle.net/10486/665349 | |
dc.description | Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. A. García Ávila Fernández, Á de Castro, Ó. Muñoz García, and F. J. Azcondo, "Pre-calculated duty cycle control implemented in FPGA for power factor correction", 35th Annual Conference of IEEE Industrial Electronics, 2009. IECON '09, Porto (Portugal), 2009, pp. 2955 - 2960 | en_US |
dc.description.abstract | A power factor correction (PFC) technique based on pre-calculated duty cycle values is presented in this paper. In this method the duty ratios for half a line period are calculated in advance and stored in a memory. By synchronizing the memory with the line, near unity power factors can be achieved in a specific operating point. The main advantage of this technique is that neither current measurement nor current loop are needed. To obtain stable output voltages a voltage loop is included. A boost converter prototype controlled by an FPGA evaluation board has been implemented in order to verify the functionality of the proposed method. Both the simulation and experimental results show that near unity power factor can be achieved with this PFC strategy. | en_US |
dc.format.extent | 7 pág. | es_ES |
dc.format.mimetype | application/pdf | en |
dc.language.iso | eng | en |
dc.publisher | Institute of Electrical and Electronics Engineers | en_US |
dc.relation.ispartof | IEEE Industrial Electronics Society. Annual Conference. Proceedings | en_US |
dc.rights | © 2009 IEEE | en_US |
dc.subject.other | Boost converter | en_US |
dc.subject.other | Digital control | en_US |
dc.subject.other | Field programmable gate array | en_US |
dc.subject.other | Power factor correction | en_US |
dc.subject.other | Switched mode power supply | en_US |
dc.title | Pre-calculated duty cycle control implemented in FPGA for power factor correction | en_US |
dc.type | conferenceObject | en |
dc.type | bookPart | en |
dc.subject.eciencia | Informática | es_ES |
dc.subject.eciencia | Telecomunicaciones | es_ES |
dc.relation.publisherversion | http://dx.doi.org/10.1109/IECON.2009.5415383 | |
dc.identifier.doi | 10.1109/IECON.2009.5415383 | |
dc.identifier.publicationfirstpage | 2955 | |
dc.identifier.publicationlastpage | 2960 | |
dc.relation.eventdate | November 3-5, 2009 | en_US |
dc.relation.eventnumber | 35 | |
dc.relation.eventplace | Porto (Portugal) | en_US |
dc.relation.eventtitle | 35th Annual Conference of IEEE Industrial Electronics, IECON 2009 | en_US |
dc.type.version | info:eu-repo/semantics/acceptedVersion | en |
dc.contributor.group | Laboratorio de Tecnología Hombre-Computador (ING EPS-010) | es_ES |
dc.rights.accessRights | openAccess | en |
dc.facultadUAM | Escuela Politécnica Superior | |