A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation
EntityUAM. Departamento de Ingeniería Informática
PublisherInstitute of Electrical and Electronics Engineers
10.1109/ICECS.1999.8122686th IEEE International Conference on Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. Volumen 1, IEEE, 1999. 241-244.
NotePersonal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. M. M. Peiró, J. Valls, T. Sansaloni, A. P. Pascual, and E. I. Boemo, "A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation", in 6th IEEE International Conference on Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99, 2009, p. 241 - 244
Rights© 1999 IEEE
In this paper, several bit-serial, high-order implementations of cascade, lattice and direct-form FIR filters using Distributed Arithmetic (DA) are studied. Although lattice and cascade structures present many interesting properties related to quantification error and stability, the DA versions have not been thoroughly compared. Three types of filters with their particular bit-serial DA model error have been built using an ALTERA 10K50 FPGA and their area-time figure is analysed. The results show that a 60th order bit-serial cascade and direct-form implementation at nearly 4 MHz and a 40th order lattice structure at 7.5 MHz can be implemented. Moreover, the lattice filter presents the lower quantification error
Google Scholar:Peiró, Marcos M. - Valls, Javier - Sansaloni, T. - Pascual, A.P. - Boemo Svcalvinoni, Eduardo Iván
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