Mañana, JUEVES, 24 DE ABRIL, el sistema se apagará debido a tareas habituales de mantenimiento a partir de las 9 de la mañana. Lamentamos las molestias.

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dc.contributor.authorPeiró, Marcos M.
dc.contributor.authorValls, Javier
dc.contributor.authorSansaloni, T.
dc.contributor.authorPascual, A.P.
dc.contributor.authorBoemo Svcalvinoni, Eduardo Iván 
dc.contributor.otherUAM. Departamento de Ingeniería Informáticaes_ES
dc.date.accessioned2015-06-22T13:24:26Z
dc.date.available2015-06-22T13:24:26Z
dc.date.issued1999
dc.identifier.citation6th IEEE International Conference on Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. Volumen 1, IEEE, 1999. 241-244.en_US
dc.identifier.isbn0-7803-5682-9
dc.identifier.urihttp://hdl.handle.net/10486/666959
dc.descriptionPersonal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. M. M. Peiró, J. Valls, T. Sansaloni, A. P. Pascual, and E. I. Boemo, "A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation", in 6th IEEE International Conference on Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99, 2009, p. 241 - 244en_US
dc.description.abstractIn this paper, several bit-serial, high-order implementations of cascade, lattice and direct-form FIR filters using Distributed Arithmetic (DA) are studied. Although lattice and cascade structures present many interesting properties related to quantification error and stability, the DA versions have not been thoroughly compared. Three types of filters with their particular bit-serial DA model error have been built using an ALTERA 10K50 FPGA and their area-time figure is analysed. The results show that a 60th order bit-serial cascade and direct-form implementation at nearly 4 MHz and a 40th order lattice structure at 7.5 MHz can be implemented. Moreover, the lattice filter presents the lower quantification erroren_US
dc.format.extent5 pág.es_ES
dc.format.mimetypeapplication/pdfen
dc.language.isoengen
dc.publisherInstitute of Electrical and Electronics Engineersen_US
dc.rights© 1999 IEEEen_US
dc.titleA comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementationen_US
dc.typeconferenceObjecten
dc.typebookParten
dc.subject.ecienciaInformáticaes_ES
dc.subject.ecienciaTelecomunicacioneses_ES
dc.relation.publisherversionhttp://dx.doi.org/10.1109/ICECS.1999.812268
dc.identifier.doi10.1109/ICECS.1999.812268
dc.identifier.publicationfirstpage241
dc.identifier.publicationlastpage244
dc.identifier.publicationvolume1
dc.relation.eventdateSeptember 5-8, 1999en_US
dc.relation.eventnumber6
dc.relation.eventplacePafos (Greece)en_US
dc.relation.eventtitle6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999en_US
dc.type.versioninfo:eu-repo/semantics/acceptedVersionen
dc.contributor.groupSistemas Digitales (ING EPS-007)es_ES
dc.rights.accessRightsopenAccessen
dc.authorUAMBoemo Svcalvinoni, Eduardo Iván (259594)
dc.facultadUAMEscuela Politécnica Superior


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