Design and FPGA implementation of digit-serial FIR filters
Entity
UAM. Departamento de Ingeniería InformáticaPublisher
Institute of Electrical and Electronics EngineersDate
1998Citation
IEEE International Conference on Electronics, Circuits and Systems, 1998. Volumen 2, IEEE, 1998. 191-194.ISBN
0-7803-5008-1DOI
10.1109/ICECS.1998.814860Editor's Version
http://dx.doi.org/10.1109/ICECS.1998.814860Subjects
Informática; TelecomunicacionesNote
Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. J. Valls, M. Martínez Peiró, T. Sansaloni, and E. Boemo, "Design and FPGA implementation of digit-serial FIR filters", in IEEE International Conference on Electronics, Circuits and Systems, 1998, p. 191 - 194Rights
© 1998 IEEEAbstract
In this paper the design of a family of digit-serial 8th-order FIR filters with programmable coefficients is presented. Both input data and coefficient size are 8 bits, but every filter of the family allows the computation with full precision of the intermediate data. The output data is truncated to 8 bits. The design of both, the digit-serial multiple precision multiply-and-accumulate and the digit-serial multiple-to-single precision converter, is detailed. All filters were implemented using an ALTERA FPGA being useful in applications with sample rate range from 5 to 22 MHz
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Google™ Scholar:Valls, Javier
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Peiró, Marcos M.
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Sansaloni, T.
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Boemo Svcalvinoni, Eduardo Iván
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