Some notes on power management on FPGA-based systems
EntityUAM. Departamento de Ingeniería Informática
PublisherSpringer Berlin Heidelberg
10.1007/3-540-60294-1_108Field-Programmable Logic and Applications: 5th International Workshop, FPL '95 Oxford, United Kingdom, August 29–September 1, 1995 Proceedings. Lecture Notes in Computer Science, Volumen 975. Springer, 1995. 149-157
ISSN0302-9743 (print); 1611-3349 (online)
ISBN978-3-540-60294-1 (print); 978-3-540-44786-3 (online)
Funded byThis work has been supported by the CICYT of Spain under contract TIC92-0083. The authors wish to thank Seamus McQuaid for his constructive comments
SubjectsLogic Design; Electronics and Microelectronics, Instrumentation; Communications Engineering, Networks; Informática; Telecomunicaciones
NoteThe final publication is available at Springer via http://dx.doi.org/10.1007/3-540-60294-1_108
Rights© Springer-Verlag Berlin Heidelberg 1995
Although the energy required to perform a logic operation has continuously dropped at least by ten orders of magnitude since early vacuum-tube electronics , the increasing clock frequency and gate density of the current integrated circuits has appended power consumption to traditional design trade-offs. This paper explore the usefullness of some low-power design methods based on architectural and implementation modifications, for FPGA-based electronic systems. The contribution of spurious transitions to the overal consumption is evidenced and main strategies for its reduction are analized. The efectiveness of pipelining and partitioning inprovements as low-power design methodologies are quantified by case-studies based on array multipliers. Moreover, a methodology suitable for FPGAs power analysis is presented.
Google Scholar:Boemo Svcalvinoni, Eduardo Iván - González de Rivera Peces, Guillermo José - López Buedo, Sergio - Meneses, Juan M.
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