A tool for activity estimation in FPGAs
Entity
UAM. Departamento de Ingeniería InformáticaPublisher
Springer Berlin HeidelbergDate
2002Citation
10.1007/3-540-46117-5_36
Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream: 12th International Conference, FPL 2002 Montpellier, France, September 2–4, 2002 Proceedings. Lecture Notes in Computer Science, Volumen 2438. Springer, 2002. 340-349.
ISSN
0302-9743 (print); 1611-3349 (online)ISBN
978-3-540-44108-3 (print); 978-3-540-46117-3 (online)DOI
10.1007/3-540-46117-5_36Funded by
Spanish Ministry of Science and Technology has supported this work, under Contract TIC2001-2688-C03-03. Additional funds have been obtained from Project 658001 of the Fundación General de la Universidad Autónoma de Madrid. G. Sutter and E. Todorovich are granted by CONICET of Argentine.Editor's Version
http://dx.doi.org/10.1007/3-540-46117-5_36Subjects
Logic Design; Memory Structures; Processor Architectures; Informática; TelecomunicacionesNote
The final publication is available at Springer via http://dx.doi.org/10.1007/3-540-46117-5_36Rights
© Springer-Verlag Berlin Heidelberg 2002Abstract
In this paper, an activity estimation tool for FPGA-based combinational circuits is presented. The current version is able to estimate average activity for individual nodes. The tool is statistical-based, allowing the user to specify the tolerated error at a given confidence level. The tunable properties of the implemented technique have been carefully tested, demonstrating how the designer can control the accuracy-speed trade-off. The importance of a realistic input pattern characterization has also been verified.
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Google Scholar:Todorovich, Elías
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Gilabert, M.
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Sutter Capristo, Gustavo Daniel
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López Buedo, Sergio
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Boemo Svcalvinoni, Eduardo Iván
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