Accurate and affordable packet-train testing systems for multi-gigabit-per-second networks
EntidadUAM. Departamento de Tecnología Electrónica y de las Comunicaciones
EditorInstitute of Electrical and Electronics Engineers Inc.
Fecha de edición2016-03-16
10.1109/MCOM.2016.7432152IEEE Communications Magazine 54.3 (2016): 80-87
ISSN0163-6804 (print); 1558-1896 (online)
Financiado porThis work was partially supported by the Spanish Ministry of Economy and Competitiveness under the project PackTrack (TEC2012-33754) and by the European Union through the Integrated Project (IP) IDEALIST under grant agreement FP7-317999
ProyectoGobierno de España. TEC2012-33754; info:eu-repo/grantAgreement/EC/FP7/317999
Versión del editorhttp://dx.doi.org/10.1109/MCOM.2016.7432152
MateriasEngineering controlled terms; Costs; Field programmable gate arrays (FPGA); Hardware; High level synthesis; Open source software; Reconfigurable hardware; Acquisition costs; Competitive costs; Development platform; Multi-gigabits; Network devices; Open source platforms; Software-based solutions; Testing systems; Engineering main heading; System-on-chip; Telecomunicaciones
NotaPersonal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. M. Ruiz, J. Ramos, G. Sutter, J. E. Lopez de Vergara, S. Lopez-Buedo and J. Aracil, "Accurate and affordable packet-train testing systems for multi-gigabit-per-second networks," in IEEE Communications Magazine, vol. 54, no. 3, pp. 80-87, March 2016. doi: 10.1109/MCOM.2016.7432152
Derechos© 2016 IEEE
Communication networks these days face a relentless increase in traffic load. Multi-gigabit-per-second links are becoming widespread, and network devices are under continuous stress, so testing whether they guarantee the specified throughput or delay is a must. Software-based solutions, such as packet-train traffic injection, were adequate for lower speeds, but they have become inaccurate in the current scenario. Hardware-based solutions have proved to be very accurate, but usually at the expense of much higher development and acquisition costs. Fortunately, new affordable FPGA SoC devices, as well as high-level synthesis tools, can very efficiently reduce these costs. In this article we show the advantages of hardware-based solutions in terms of accuracy, comparing the results obtained in an FPGA SoC development platform and in NetFPGA-10G to those of software. Results show that a hardware-based solution is significantly better, especially at 10 Gb/s. By leveraging high-level synthesis and open source platforms, prototypes were quickly developed. Noticeable advantages of our proposal are high accuracy, competitive cost with respect to the software counterpart, which runs in high-end off-the-shelf workstations, and the capability to easily evolve to upcoming 40 Gb/s and 100 Gb/s networks.
Google Scholar:Ruiz, Mario - Ramos, Javier - Sutter Capristo, Gustavo Daniel - López de Vergara Méndez, Jorge Enrique - López Buedo, Sergio - Aracil, Javier
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