Comparison of power converter models with losses for hardware-in-the-loop using different numerical formats
EntityUAM. Departamento de Tecnología Electrónica y de las Comunicaciones
10.3390/electronics8111255Electronics 8.11 (2019): art.1255
Funded byThis research was funded by Spanish Ministerio de Economía y Competitividad grant number TEC2013-43017-R
ProjectGobierno de España. TEC2013-43017-R
SubjectsHardware in the loop; Numerical format; Field programmable gate array; Telecomunicaciones
Rights© 2019 by the authors
Esta obra está bajo una Licencia Creative Commons Atribución 4.0 Internacional.
Nowadays, the Hardware-In-the-Loop (HIL) technique is widely used to test different power electronic converters. These real-time simulations require processing large data at high speed, which makes this application very suitable for FPGAs (Field Programmable Gate Array) as they are capable of parallel processing. This paper provides an analytical discussion on three HIL models for a full-bridge converter. The three models use different possible numerical formats, namely float and fixed-point, the latter with and without optimizing the width of signals to the embedded DSP (Digital Signal Processors) blocks of the FPGA. The optimized fixed-point model (OFPM) uses three and two times fewer DSP blocks or LUTs (Look Up Tables), and the maximum achievable clock frequency is also up to 35 % and 25 % higher than the float model and non-optimized fixed-point model (nOFPM), respectively. Furthermore, the models’ accuracy is proportional to the clock frequency, thus the OFPM is also the most accurate model. Finally, the paper shows the differences in the simulation when the models include or not losses, proving that not including losses leads to high errors, especially during transients
Google Scholar:Zamiri Mamooliraftar, Elyas - Sánchez González, Alberto - Castro Martín, Ángel de - Martínez García, María Sofía
This item appears in the following Collection(s)
Showing items related by title, author, creator and subject.