Analysis of resolution in feedback signals for hardware-in-the-loop models of power converters
Entity
UAM. Departamento de Tecnología Electrónica y de las ComunicacionesPublisher
MDPI, Basel, Switzerland.Date
2019-12-19Citation
10.3390/electronics8121527
Electronics 8 (2019): 1527
ISSN
2079-9292DOI
10.3390/electronics8121527Editor's Version
https://doi.org/10.3390/electronics8121527Subjects
Hardware-in-the-loop; Resolution; Fixed-point; Feedback; State variables; InformáticaRights
© 2019 by the authorsAbstract
One of the main techniques for debugging power converters is hardware-in-the-loop (HIL),
which is used for real-time emulation. Field programmable gate arrays (FPGA) are the most common
design platforms due to their acceleration capability. In this case, the widths of the signals have to be
carefully chosen to optimize the area and speed. For this purpose, fixed-point arithmetic is one of the
best options because although the design time is high, it allows the personalization of the number of
bits in every signal. The representation of state variables in power converters has been previously
studied, however other signals, such as feedback signals, can also have a big influence because they
transmit the value of one state variable to the rest, and vice versa. This paper presents an analysis of
the number of bits in the feedback signals of a boost converter, but the conclusions can be extended to
other power converters. The purpose of this work is to study how many bits are necessary in order to
avoid the loss of information, but also without wasting bits. Errors of the state variables are obtained
with di erent sizes of feedback signals. These show that the errors in each state variable have similar
patterns. When the number of bits increases, the error decreases down to a certain number of bits,
where an almost constant error appears. However, when the bits decrease, the error increases linearly.
Furthermore, the results show that there is a direct relation between the number of bits in feedback
signals and the inputs of the converter in the global error. Finally, a design criterion is given to choose the optimum width for each feedback signal, without wasting bits
Files in this item
Google Scholar:Martínez García, María Sofía
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Castro Martín, Ángel de
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Sánchez González, Alberto
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Garrido Salas, Javier
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