Enhancing conditional stalling to boost performance of stream-processing logic with RAW dependencies
Entity
UAM. Departamento de Tecnología Electrónica y de las ComunicacionesPublisher
IEEEDate
2023-01-18Citation
10.1109/TCSII.2023.3237736
IEEE Transactions on Circuits and Systems II: Express Briefs 70. 7 (2023): 2620- 2624
ISSN
1549-7747 (print); 1558-3791 (online)DOI
10.1109/TCSII.2023.3237736Funded by
This work was supported in part by the Spanish Research Agency through the Project AgileMon under Grant AEI PID2019-104451RB-C21Project
Gobierno de España. PID2019-104451RB-C21Editor's Version
https://doi.org/10.1109/TCSII.2023.3237736Subjects
hardware design; high-level synthesis; latency masking; read-after-write dependency; runtime optimization; TelecomunicacionesRights
© 2023 The authorsEsta obra está bajo una licencia de Creative Commons Reconocimiento-NoComercial-SinObraDerivada 4.0 Internacional.
Abstract
Ambiguous read-after-Write (RAW) dependencies are omnipresent in multiple streaming applications, establishing hard to optimize bottlenecks. Considering actual input data, these may rarely be true dependencies. However, the increasingly used High-Level Synthesis (HLS) compilers must assume the worst-case scenario, as they rely on static optimizations. Conditional stalling is a simple yet impactful technique, useful even when conflicts are common. At the cost of a small area penalty, it allows improving (in some cases, by several times) the mean throughput of these systems. In this brief, we describe a high-frequency HLS implementation of the technique and examine its behavior as a function of input and architecture characteristics, with the goal of understanding when to use it and how to optimize throughput
Files in this item
Google Scholar:Alonso, Tobías
-
Sutter Capristo, Gustavo Daniel
-
López Buedo, Sergio
-
López de Vergara Méndez, Jorge Enrique
This item appears in the following Collection(s)
Related items
Showing items related by title, author, creator and subject.